1. Field of the Invention
Embodiments of the present invention relate to a semiconductor device, and more particularly to a semiconductor device that includes a data input circuit that writes a plurality of write data sets that are supplied in serial to a memory cell array in parallel.
2. Description of Related Art
DRAM (Dynamic Random Access Memory) that is one of typical semiconductor storage devices generally includes a DLL (Delay Locked Loop) circuit to accurately perform high-speed data transfer with a memory controller. The DLL circuit generates a phase-controlled internal clock signal based on an external clock signal supplied from the memory controller. Because read data is output in synchronization with the phase-controlled internal clock signal, high-speed data transfer can be performed accurately.
However, the DLL circuit consumes relatively large amounts of power. Therefore, especially DRAMs that are required to consume small amounts of power for use in mobile devices may not include a DLL circuit. In the DRAM of this type, read data that has been parallel-to-serial converted by using an internal clock signal not phase-controlled is output to outside without being phase-controlled. Even during a writing operation, write data that has been input in synchronization with a data strobe signal is serial-to-parallel converted by using an internal clock signal not phase-controlled (See Japanese Patent Application Laid-Open No. 2011-108300).
Some of the DRAMs for mobile devices and the like adopt an edge-pad-type layout in which external terminals are arranged along two edges, that face each other, of a semiconductor chip. In this case, pads for command address signals are arranged along one edge of the two edges, and pads for data signals are arranged along the other edge of the two edges (See Japanese Patent Application Laid-Open No. 2011-108352).
However, in a semiconductor device having an edge-pad-type layout, peripheral circuits that perform command address operations are disposed away from peripheral circuits that perform data transfer operations. As a result, the length of a signal line is very long to connect those peripheral circuits. Accordingly, the signal line has a relatively large parasitic capacitance. Therefore, a charge-and-discharge current to drive the signal line becomes larger, and the amount of current consumed is increased.